BIB-VERSION:: CS-TR-v2.0
          ID:: STAN//CS-TR-89-1266
       ENTRY:: January 05, 1995
ORGANIZATION:: Stanford University, Department of Computer Science
       TITLE:: Multi-level shared caching techniques for scalability in
               VMP-MC
        TYPE:: Technical Report
      AUTHOR:: Cheriton, David R.
      AUTHOR:: Goosen, Hendrik A.
      AUTHOR:: Boyle, Patrick D.
        DATE:: May 1989
       PAGES:: 20
    ABSTRACT:: The problem of building a scalable shared memory
               multiprocessor can be reduced to that of building a scalable
               memory hierarchy, assuming interprocessor communication is
               handled by the memory system. In this paper, we describe the
               VMP-MC design, a distributed parallel multi-computer based on
               the VMP multiprocessor design, that is intended to provide a
               set of building blocks for configuring machines from one to
               several thousand processors. VMP-MC uses a memory hierarchy
               based on shared caches, ranging from on-chip caches to
               board-level caches connected by busses to, at the bottom, a
               high-speed fiber optic ring. In addition to describing the
               building block components of this architecture, we identify
               the key performance issues associated with the design and
               provide performance evaluation of these issues using
               trace-drive simulation and measurements from the VMP.
       NOTES:: [Adminitrivia V1/RAM/19950105]
         END:: STAN//CS-TR-89-1266